1. Field of the Invention
The present invention relates to a non-volatile memory and an operation method thereof. More particularly, the present invention relates to a non-volatile memory and an operation method thereof including a multi-level cell having a plurality of storage positions.
2. Description of Related Art
A nitride read only memory (NBit) is a nitride structure memory using silicon nitride as a charge trapping layer instead of using a polysilicon floating gate, in which a single NBit memory cell may have two separated charge bits according to a localized charge trapping technique, so as to form a so-called 2 bits/cell storage scheme. Moreover, by respectively program the two bits of the NBit memory cell to a plurality of levels, the NBit memory cell can also serve as a multi-level cell (MLC).
When the NBit memory cell is operated, the two bits in a same memory cell can influence each other to generate a read error problem. In brief, if one side of the NBit memory cell is stored with a bit, the other side of the NBit memory cell is read, and a current of an originally high current part can be decreased, which may lead to a so-called second-bit effect. Namely, when a read operation is performed to the NBit memory cell, the originally existed bit can influence the memory cell to increase a read threshold voltage (Vt). In this case, the read error problem is probably occurred.
FIG. 1 is a diagram illustrating a threshold voltage distribution of a conventional nitride structure MLC. As shown in FIG. 1, curves 110-140 are threshold-voltage distribution curves when a state of the memory cell is respectively level 1 to level 4. Wherein, if a first storage position of the NBit memory cell is maintained to the level 1, a second storage position of the NBit memory cell is programmed to the level 2, and the threshold voltage distribution curve of the first storage position maintained to the level 1 is shifted due to the second-bit effect, and a shift amount thereof is shown as a curve 150. Similarly, curves 160 and 170 respectively represent the shift amount of the threshold voltage distribution curve of the first storage position maintained to the level 1 that is generated due to the second-bit effect, when the second storage position of the NBit memory cell is respectively programmed to the level 3 and the level 4.
As shown in FIG. 1, the higher level the second storage position is programmed, the more severe the second-bit effect is. For example, when the second storage position is programmed to the level 4, the threshold voltage shift curve 170 of the first storage position generated due to the second-bit effect is very closed to the threshold voltage distribution curve 120 programmed to the level 2. Now, if the NBit memory cell is read, the level 1 first storage position can be misjudged to be level 2, so that device reliability is decreased. Moreover, the second-bit effect further reduces a read sense margin of the memory and a threshold-voltage window for operating the right and left bits, so that operation of the MLC can be more difficult.